Critical design issues for gallium arsenide VLSI circuits.

The aim of this research was to design and evaluate various Gallium Arsenide circuit elements such as logic gates, adders and multipliers suitable for high speed VLSI circuits. The issues addressed are the logic gate design and optimisation, evaluation of various buffering schemes and the impact of the algorithm on adder and multiplier performance for digital signal processing applications. This has led to the development of a design approach to produce high speed and low power dissipation Gallium Arsenide VLSI circuits. This is achieved by :
Evaluating the well established Direct Coupled Logic (DCFL) gates and proposing an alternative gate, namely the Source Follower DCFL (SDCFL), to improve the noise margin and speed.
Suggesting various buffering schemes to maintain high speed in areas where the fanout loading is high (eg. clock drivers).
Comparing various adder types in terms of delay-power and delay-area products to arrive at a suitable architecture for Gallium Arsenide implementation and to determine the influence of the algorithm and layout approach on circuit performance. To investigate this further, a multiplier was also designed to assess the performance at higher levels
of integration.
Applying a new layout approach, called the 'ring notation*, to the adder and multiplier circuits in order to improve their delay-area product.
Finally, the critical factors influencing the performance of the circuits are reviewed and a number of suggestions are given to maintain reliable operation at high speed.