A hardware accelerated semi analytic approach for fault trees with repairable ccmponents.

Fault tree analysis of complex systems with
repairable components can easily be quite complicated
and usually requires significant computer time and
power despite significant simplifications. Invariably,
software-based solutions, particularly those involving
Monte Carlo simulation methods, have been used in
practice to compute the top event probability.
However, these methods require significant computer
power and time. In this paper, a hardware-based
solution is presented for solving fault trees. The
methodology developed uses a new semi analytic
approach embedded in a Field Programmable Gate
Array (FPGA) using accelerators. Unlike previous
attempts, the methodology developed properly handles
repairable components in fault trees. Results from a
specially written software-based simulation program
confirm the accuracy and validate the efficacy of the
hardware-oriented approach.

Conference held in Cambridge, 25th-27th May, 2009