Wafer-scale integration of semiconductor memory.

PhD thesis


Aubusson, R. 1979. Wafer-scale integration of semiconductor memory. PhD thesis Middlesex Polytechnic Engineering
TypePhD thesis
TitleWafer-scale integration of semiconductor memory.
AuthorsAubusson, R.
Abstract

This work is directed towards a study of full-slice or "wafer-scale integrated" - semiconductor memory. Previous approaches to full slice technology are studied and critically compared. It is shown that a fault-tolerant, fixed-interconnection approach offers many advantages; such a technique forms the basis of the experimental work. The
disadvantages of the conventional technology are reviewed to illustrate the potential improvements in cost, packing density and reliability obtainable with wafer-scale
integration (W.S.l).
Iterative chip arrays are modelled by a pseudorandom fault distribution; algorithms to control the linking of adjacent good - chips into linear chains are proposed and
investigated by computer simulation. It is demonstrated that long chains may be produced at practicable yield levels. The on-chip control circuitry and the external control electronics required to implement one particular algorithm are described in relation to a TTL simulation of an array of 4 X 4 integrated circuit chips. A layout of the on-chip control logic is shown to require (in 40 dynamic MOS circuitry) an area equivalent to ~250 shift register stages -a reasonable overhead on large memories.
Structures are proposed to extend the fixed-interconnection, fault-tolerant concept to parallel/serial organised memory - covering RAM, ROM and Associative Memory
applications requiring up to~ 2M bits of storage. Potential problem areas in implementing W.S.I are discussed and it is concluded that current technology is capable of manufacturing such devices. A detailed cost comparison of the conventional and W.S.I approaches to large serial memories illustrates the potential savings available with wafer-scale integration.
The problem of gaining industrial acceptance for W.S.I is discussed in relation to known and anticipated views- of new technology. The thesis concludes with suggestions for
further work in the general field of wafer-scale integration.

Department nameEngineering
Institution nameMiddlesex Polytechnic
Publication dates
Print12 Aug 2011
Publication process dates
Deposited12 Aug 2011
CompletedApr 1979
Output statusPublished
Additional information

Thesis submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy.

LanguageEnglish
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