An FPGA-based divider circuit using simulated annealing algorithm

Conference paper


Sworna, Z., Haque, M. and Rahman, S. 2018. An FPGA-based divider circuit using simulated annealing algorithm. ISCIT 2018 - 18th International Symposium on Communications and Information Technologies. Bangkok, Thailand 26 - 29 Sep 2018 IEEE. pp. 241-246 https://doi.org/10.1109/ISCIT.2018.8588004
TypeConference paper
TitleAn FPGA-based divider circuit using simulated annealing algorithm
AuthorsSworna, Z., Haque, M. and Rahman, S.
Abstract

Division is considered as the slowest and most difficult operation among four basic operations in microprocessors. This paper proposes a unique division algorithm using a new approach of simulated annealing algorithm. A heuristic function is proposed to determine the global and local optimum value, whereas the conventional approaches use random values to reach the target value. In addition, a new temperature schedule is introduced for faster computation of global maxima/minima. The proposed simulated annealing performs better than the best known existing method of simulated annealing algorithm for smooth energy landscape due to the introduction of a new goal-based temperature. Thus, the proposed division algorithm computes the current partial remainder and quotient bits simultaneously per iteration which reduces the delay of the proposed divider circuit significantly. Moreover, the proposed divider circuit requires only two operations per iteration, whereas the exiting best one requires three operations per iteration. The proposed divider circuit is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a -3 speed grade by using ISE 13.1. The proposed divider circuit achieves an improvement of 36.17% and 44.67% respectively in terms of LUTs and delay factor for a 256 by 128 bit division over the best known contemporary FPGA-based divider circuit. It can be used into the designs of arithmetic logic unit, image processing and robotics system. The experimental result indicates that the divider takes fewer resources, and its performance is steady and reliable.

ConferenceISCIT 2018 - 18th International Symposium on Communications and Information Technologies
Page range241-246
Proceedings Title2018 18th International Symposium on Communications and Information Technologies (ISCIT)
ISBN
Hardcover9781538684580
Hardcover9781538659847
PublisherIEEE
Publication dates
Print26 Sep 2018
Online27 Dec 2018
Publication process dates
Deposited17 Apr 2020
Accepted21 Aug 2018
Output statusPublished
Accepted author manuscript
Copyright Statement

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Digital Object Identifier (DOI)https://doi.org/10.1109/ISCIT.2018.8588004
LanguageEnglish
Book title2018 18th International Symposium on Communications and Information Technologies (ISCIT)
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